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SOCkit-CYCLONE EP1C6


SOCkit-Cyclone™ EP1C6 Evaluation Package

Information :

The SOCkit evaluation board provides all the “essentials” for properly implementing a compact and cost effective Altera® Cyclone™ and Nios II embedded processor design.  This design utilizes Altera's latest low cost EPCSx series of serial flash configuration devices.  The SOCkit can use this serial flash for FPGA initialization, software boot, and non-volatile data storage.  The SOCkit design also provides high-speed LVDS interfaces, and one RS-232C interface.  The SOCkit hardware platform can be used to tinker with many of the other HDL IP processor cores that are available (8051, Z80, etc).

PCB Hardware Components :

  1. Altera EP1C6 Cyclone FPGA
     
  2. 128K x 8 bit SRAM.
     
  3. EPCS4 serial flash
     
  4. Dual ByteBlaster II programming ports (ASMI flash and JTAG interface).
     
  5. LCD interface and 2 line X 16 character LCD display
     
  6. Reset, menu, and select buttons
     
  7. 8 channel LVDS and one RS232 interface
     
  8. Up to 94 FPGA IO available on header pins.
     
  9. 6 discrete indicator LED
     
  10. 4 position dip-switch
     
  11. Clock oscillator

FPGA/Nios II Reference Design Features  :

  1. Created using Quartus II 6.0 SP2.

  2. VDS pattern generation and detection with byte error rate. 

  3. 32 bit Nios II processor supporting interrupts, timer, UART, and PIO.

  4. Configurable Nios II software boot using JTAG debugger or EPCS4 image copy to SRAM

  5. Nios II program execution from external 128K X 8 bit SRAM.

  6. EPCS4 nonvolatile flash data storage.

  7. LCD menu operation.

  8. LED test


Kit Package Contents
:

  1. SOCkit evaluation board

  2. External 16 character X 2 line LCD module

  3. 14 pin LCD ribbon cable

  4. LVDS patch cable

  5. Wall mount 5VDC/2A switching power supply

  6. DB-9 RS232 cable

  7. Altera ByteBlaster II FPGA programmer

  8. Altera Quartus II “web-pack” tools CD 6.1

  9. SOCkit data files CD

Note:  Some user modifications of the SOCkit Nios II design may be required to support compilation under later versions of Quartus II.  Quartus II "web edition" software CD is version 6.1.  Later Quartus II versions require download from the Altera website.

Downloads :

SOCkit User Guide 
       (1.6M
B)

SOCkit Brochure
       (360 KB)


Powertip LCD Display Specification
    
  (1.5 MB)

SOCkit Project Setup Readme File
       (76KB)


Product Data :

FPGA EP1C6
Logic Elements (apprx. 50 gates per LE) 5,980
RAM Blocks (4 Kbits + parity) 20
RAM Bits 92,160
PLLs 2

 

SOCkit-6 - PCB contains the EP1C6 FPGA, -6 speed grade, 144 pin TQFP package, up to 312Mbs LVDS data rate.  $329.00 package, $249.00 circuit card (and one LVDS cable for loop-back testing)


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