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CMCS002


CMCS002 Controller/FPGA Module

Information :

The CMCS002 module allows implementation of general logic functions and/or Altera® Nios II processor operation in a compact form factor module.  The module provides the following circuits to support an FPGA based controller:
 

  Altera EP3C25 FPGA
   512K X 8 SRAM
   EP1S16 FPGA serial loader (FPGA and Nios II boot)
  USB 2.0 Peripheral Port (low/full speed operation)


The CMCS002 module also supports the specification (master or slave standard card, 128 pin), and can interface with other modules designed to that specification.  The CMCS002 kit includes an FPGA programmer and power supply, and provides all the hardware items which are necessary to start designing with and evaluating the powerful features of Altera® Cyclone III FPGA devices.

Module Details :

  1. Altera® EP3C25 FPGA, in –C8 speed grade in 256 pin BGA package.
  2. Separate programming ports (ASMI flash interface and JTAG interface).
  3. Reset and voltage monitor IC which provides 400mS reset pulse.
  4. Reset push-button switch.
  5. 109 input/output pins available on stack-through header.
  6. 3 discrete indicator LED (red, yellow, green).
  7. Clock oscillator (25 MHz).
  8. compatible design.  Populated with stack-through connector.
  9. EPCS16 (16Mbit) serial flash for FPGA configuration and Nios II software.
  10. 512K x 8 bit (4Mbit) SRAM for Nios II program execution and dynamic data storage.
  11. USB 2.0 full speed port (FT232RL).

Quartus II Starter Design :

  1. Created using Quartus II ver. 9.0 SP1.

  2. Nios II processor defined.

  3. All module pins are defined in top level schematic project file. 

  4. Memory test with results indicated to LED.

  5. FPGA load from EPCS16.

Kit Package Contents :

  1. CMCS002 Cyclone III EP3C25 module.

  2. Wall mount 3.3VDC/2A switching supply.

  3. Altera® ByteBlaster II FPGA programmer (USB blaster kit also available).

 


Support Files :

- CMCS002-2M User Guide Rel. 2
          (400 KB)

- CMCS002-2M Rev. A Schematic
          (1.0 MB)

- Nios/Quartus Starter Design Q9.0 SP2 
          (1.3 MB) - Includes Nios II processor

- Quartus Starter Design Q9.0 SP1 
          (167 KB) - stand-alone version, no Nios II

- NiosII Design Readme
          (544 KB)
- Pin information spread-sheet
       (23 KB)

Please email us at requests@dallaslogic.com to request these files.

Note:  The starter design available for this FPGA module was created using Quartus II ver. 9.0 SP1.  Some user modification of the starter design may be required to support compilation under later versions of Quartus II.  Quartus II "web edition" is available for download from the Altera website. This starter design is provided "as is".  Modification or support of this Nios II starter design is not included in the purchase price.


Images :

    

    


Product Data :

 
FPGA EP3C25
Logic Elements (apprx. 50 gates per LE) 24624
M9K RAM Blocks (9216 bits per block) 66
RAM (K bits) 594
PLLs 4
18 bit x 18 bit Multipliers 66

 

CMCS002-2M-8 EP3C25 module 249.00 US
CMCS002-2M-8-KB EP3C25 Byte Blaster kit 359.00
CMCS002-2M-8-KU EP3C25 USB Blaster kit 489.00

Unit quantity discounts are applied to your online order.  See the order page for details.



 
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