IMPORTANT: Never connect ezFPGA IO pins directly to 5V devices. Always use a current limiting series resistor. See User Manual for details. ezFPGA pin FPGA pin num. Connector Pin num. Direction Notes ---------- ------------- ---------- -------- ---------- ---------------------------------------------------------------------- PWR_GNDIN J101-B1 1 pwr input Auxilliary GND input. Power input when not using the AC wall adapter. PWR_VIN J101-B1 2 pwr input Auxilliary 5V input. Power input when not using the AC wall adapter. VCORE J101-B1 3 pwr output Regulated VCORE voltage output, 1.5V VIO J101-B1 4 pwr output Regulated VIO voltage output, 3.3V B1_IO17 36 J101-B1 5 sig IO GND J101-B1 6 B1_IO16 35 J101-B1 7 sig IO B1_IO15 34 J101-B1 8 sig IO B1_IO14 33 J101-B1 9 sig IO GND J101-B1 10 B1_IO13 32 J101-B1 11 sig IO B1_IO12 31 J101-B1 12 sig IO B1_IO11 28 J101-B1 13 sig IO B1_IO10 27 J101-B1 14 sig IO B1_IO9 26 J101-B1 15 sig IO GND J101-B1 16 AUX_CLKIN1 17 J101-B1 17 sig input FPGA clock input pin B1_IO8 11 J101-B1 18 sig IO CLK_24MHZ 16 J101-B1 19 sig output 24 MHz oscillator output B1_IO7 10 J101-B1 20 sig IO B1_IO6 7 J101-B1 21 sig IO GND J101-B1 22 B1_IO5 6 J101-B1 23 sig IO B1_IO4 5 J101-B1 24 sig IO B1_IO3 4 J101-B1 25 sig IO GND J101-B1 26 B1_IO2 3 J101-B1 27 sig IO B1_IO1 2 J101-B1 28 sig IO B1_IO0 1 J101-B1 29 sig IO GND J101-B1 30 B2_IO24 143 J101-B2 1 sig IO B2_IO25 144 J101-B2 2 sig IO FPGA global clrn (connected to reset IC output through 1.0K ohm resistor). B2_IO22 141 J101-B2 3 sig IO B2_IO23 142 J101-B2 4 sig IO B2_IO21 140 J101-B2 5 sig IO GND J101-B2 6 B2_IO19 134 J101-B2 7 sig IO B2_IO20 139 J101-B2 8 sig IO B2_IO17 132 J101-B2 9 sig IO B2_IO18 133 J101-B2 10 sig IO B2_IO15 130 J101-B2 11 sig IO B2_IO16 131 J101-B2 12 sig IO B2_IO14 129 J101-B2 13 sig IO GND J101-B2 14 B2_IO12 125 J101-B2 15 sig IO B2_IO13 128 J101-B2 16 sig IO B2_IO10 123 J101-B2 17 sig IO B2_IO11 124 J101-B2 18 sig IO B2_IO8 121 J101-B2 19 sig IO B2_IO9 122 J101-B2 20 sig IO B2_IO7 120 J101-B2 21 sig IO GND J101-B2 22 B2_IO5 114 J101-B2 23 sig IO B2_IO6 119 J101-B2 24 sig IO B2_IO3 112 J101-B2 25 sig IO B2_IO4 113 J101-B2 26 sig IO B2_IO1 110 J101-B2 27 sig IO B2_IO2 111 J101-B2 28 sig IO B2_IO0 109 J101-B2 29 sig IO GND J101-B2 30 B3_IO21 108 J100-B3 1 sig IO Drive low to illuminate red LED. This net is driven by the reference design. GND J100-B3 2 B3_IO20 107 J100-B3 3 sig IO Drive low to illuminate yellow LED. This net is driven by the reference design. B3_IO19 106 J100-B3 4 sig IO Drive low to illuminate green LED. This net is driven by the reference design. B3_IO18 105 J100-B3 5 sig IO GND J100-B3 6 B3_IO17 104 J100-B3 7 sig IO B3_IO16 103 J100-B3 8 sig IO B3_IO15 100 J100-B3 9 sig IO GND J100-B3 10 B3_IO14 99 J100-B3 11 sig IO B3_IO13 98 J100-B3 12 sig IO B3_IO12 97 J100-B3 13 sig IO B3_IO11 96 J100-B3 14 sig IO AUX_CLKIN2 93 J100-B3 15 sig input FPGA clock input pin GND J100-B3 16 AUX_CLKIN3 92 J100-B3 17 sig input FPGA clock input pin B3_IO10 85 J100-B3 18 sig IO B3_IO9 84 J100-B3 19 sig IO B3_IO8 83 J100-B3 20 sig IO B3_IO7 82 J100-B3 21 sig IO GND J100-B3 22 B3_IO6 79 J100-B3 23 sig IO B3_IO5 78 J100-B3 24 sig IO B3_IO4 77 J100-B3 25 sig IO B3_IO3 76 J100-B3 26 sig IO B3_IO2 75 J100-B3 27 sig IO B3_IO1 74 J100-B3 28 sig IO B3_IO0 73 J100-B3 29 sig IO GND J100-B3 30 B4_IO24 71 J100-B4 1 sig IO B4_IO25 72 J100-B4 2 sig IO B4_IO22 69 J100-B4 3 sig IO B4_IO23 70 J100-B4 4 sig IO B4_IO21 68 J100-B4 5 sig IO GND J100-B4 6 B4_IO19 62 J100-B4 7 sig IO B4_IO20 67 J100-B4 8 sig IO B4_IO17 60 J100-B4 9 sig IO B4_IO18 61 J100-B4 10 sig IO B4_IO15 58 J100-B4 11 sig IO B4_IO16 59 J100-B4 12 sig IO B4_IO14 57 J100-B4 13 sig IO GND J100-B4 14 B4_IO12 53 J100-B4 15 sig IO B4_IO13 56 J100-B4 16 sig IO B4_IO10 51 J100-B4 17 sig IO B4_IO11 52 J100-B4 18 sig IO B4_IO8 49 J100-B4 19 sig IO B4_IO9 50 J100-B4 20 sig IO B4_IO7 48 J100-B4 21 sig IO GND J100-B4 22 B4_IO5 42 J100-B4 23 sig IO B4_IO6 47 J100-B4 24 sig IO B4_IO3 40 J100-B4 25 sig IO B4_IO4 41 J100-B4 26 sig IO B4_IO1 38 J100-B4 27 sig IO B4_IO2 39 J100-B4 28 sig IO B4_IO0 37 J100-B4 29 sig IO GND J100-B4 30 RESET_IN J2 3 sig input Active low reset input. This is an open drain net which drives into the reset IC. Reset IC will provide 400mS reset pulse to the FPGA global clear pin.